AMD plans on increasing the core count of its Zen 5 CPUs by dozens!


The purchase of Xilinx by AMD can be considered as one of the most important that have been made in recent years in the hardware industry and it is for Lisa Su’s company as was the purchase of ATI in the 2000s, especially in the face of scaling its processors. How does the purchase of Xilinx affect future AMD CPUs?

The history of PC CPUs can be separated into two parts: the period of single-core processors and the multi-core era in which we now find ourselves. What was the event that triggered the paradigm shift? Dennard scaling has come to an end. After more than 15 years of multi-core computers, the challenge now is to increase the number of cores beyond the present levels.

With Intel betting on heterogeneous cores of varying size, power consumption, and complexity within the single Alder Lake processor and AMD with Zen 5, it is evident that the number of cores will grow. However, as the number of processors increases, so does the complexity of the processor infrastructure.

Infrastructure complexity and power consumption

To comprehend AMD’s acquisition of Xilinx, keep in mind that the goal is to use SmartNICs, or intelligent network controllers, to govern the communication infrastructure of the various cores. But first and foremost, we must identify the issue.

If I, for example, have 4 cores, then I will only need 12 links to intercommunicate the different cores with each other, but if I have 8 cores, things get more complicated and I end up needing a total of 56 links, so imagine with a larger number of cores.


The processor-to-processor interactions not only necessitate a more complicated architecture, but these links also consume electricity. What is the solution? AMD introduced ring communication interfaces in Zen 3 to reduce cabling and connections but increase send latency.

Rumors say that Zen 4 will retain the same number of cores per CCD, which is 8, and that it will be Zen 5 that will see the integration of Xilinx’s technology into AMD CPUs with the goal of expanding the number of potential cores in a processor.

Xilinx technology will be employed in future CPUs in this manner

Xilinx technology will undoubtedly be fully utilized in AMD’s Zen 5 CPU infrastructure. A SmartNIC will be located at the processor’s core and will be in charge of receiving all communication requests between the multiple cores, which is far more efficient than using specific communication infrastructures. Let us not forget that, while some of them save on the number of connections, they add latency and are counterproductive in performance above a certain number of cores.

After all, it’s the same thing Intel did with their IPU, which will be used for the first time in Xeon Sapphire Rapids, and it’s the path that the entire industry is taking to get to the tens-of-cores age.

Then, AMD will replace the now classic “Scalable Data Fabric” as the Northbridge of its future Zen’s with an intelligent network controller from Xilinx at the core of its processors. Given that the SDF is utilised in both CPU and GPU design, the implication is that the shift will occur not only in future CPUs, but also in graphics cards, where the number of cores will undoubtedly rise and multi-chip designs will become common.

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