One of the most important points when creating new processors is not only in the design of new computing units, but also in new ways of packaging and interconnection between the different elements. A few months ago, AMD talked about its V-Cache for the first time, consisting of stacking an SRAM as LLC in a Zen 3. In the Hot Chips event, AMD have given new details of its V-Cache.
Hot Chips, a symposium where various hardware makers and designers demonstrate their latest technological developments, is taking place during these days. The difference between Hot Chips and other events is that it is not a commercial conference, so we are not at a trade exhibition, but rather an event geared for engineers and hardware enthusiasts, where the latest technological breakthroughs, their rationale, and how they work are described. As is the situation with the V-Cache, about which AMD has released additional information.
AMD has released fresh information about its V-Cache for the Zen 3
AMD stunned us all a few months back with something unexpected. The installation of an SRAM memory chip on top of the Zen 3’s Chiplet CCD, which we learnt was already planned for it from the start. The goal is to increase the capacity of the L3 cache shared by all Zen 3 cores inside the CCD chiplet, and therefore the performance.
The reason for the performance increase is very simple, with it the amount of data that is cached increases. This means that the data accessed by the RAM are reduced as there is more data in the last level cache, thus increasing performance by up to 15% without changing the rest of the chip.
What new information has AMD provided about its V-Cache? They employed numerous microbumps to communicate the SRAM module with the CCD, while the wiring is the traditional via silicon or TSV. The Chiplet CCD was vertically interconnected with the additional SRAM via dialectric-dialectric connections with direct copper-to-copper bonding. This form of connection was created in collaboration with TSMC.
The interconnect microbumps are 9 micrometers in size, which is 10% smaller than the ones utilized by Intel at Foveros for Lakefield. It should be noted that the key to vertical 3D interconnects is the number of interconnects, because the strategy to increase the bandwidth between the two parts is to increase the number of interconnects rather than the clock rate of each interconnect in order to keep the consumption for data transmission as low as possible.
V-Cache is just the beginning, AMD warns us
It is no secret that 3DIC integration of chips, including logic and memory, is the way of the future. This is demonstrated by the presence of non-monolithic configurations of the 3DIC or 2.5DIC type in various designs under development from various manufacturers.
At the moment, we only have cases of stacked memories such as V-NAND or HBM in their various flavors, but logic and memory will be available soon. However, we may see AMD designs in the near future where IOD and Chiplets are stacked on top of each other. This does not surprise us; it was expected. The difference is that AMD has just recently stated that it is working on it.
So, future CPUs based on AMD Zen 4 may not only feature V-Cache, but may also be in a 3DIC configuration or otherwise different not just from the original monolithic single-piece processors, but also from the 2.5DIC chiplet format seen in the AMD Ryzen 3000 and Ryzen 5000.