96 cores, DDR5 + PCIe 5 CPUs – AMD EPYC Leaks

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AMD EPYC “Genoa” CPUs: 96 cores, DDR5 and PCIe 5

There is still some time to go before the launch of the different CPUs based on its Zen 4 architecture since everything points to the fact that we will first see an intermediate range based on a slight improvement over Zen 3. It will be called Zen 3+ and will be manufactured at TSMC’s 6 nm node. Information about Genoa, the AMD EPYC based on Zen 4, has surfaced in the last few days.

With the recent launch of Milan, the Zen 3-based AMD EPYC, rumors about the Zen 4-based AMD EPYC under the codename Genoa has started to surface. So, AMD continues to use Italian cities for its server CPUs based on its various Zen architectures.

AMD EPYC with Zen 4 breaks with tradition

Through the tweet of one of the leakers of information, it has been possible to know new data of the configuration of the future AMD Genoa, which will compete with the Intel Xeon to be launched in 2022.

First, there has been a move from a maximum of 64 cores and 128 threads of the current AMD EPYC Milan to the 96 cores and 192 threads of the future AMD EPYC Genoa. But, what is striking is that we now have 12 channels of DDR5-5200 memory. It is not only the new type of memory that is striking, but it is also the 128 PCIe 5.0 lanes. From specific sources, we have information that both standards will arrive in full force to PCs later this year and during 2022.

What is surprising is precisely the 12 channels because the number of channels is directly proportional to the number of CCD chiplets mounted on the chip. So, we are talking about a configuration of 12 chiplets in total, so we have eight cores per CCD chiplet and not more as has been speculated.

The new information contradicts the previous ones

The IO Die used in AMD EPYC Rome and AMD EPYC Milan, Zen 2, and Zen 3, respectively, is the same and intended for DDR4, PCIe 4.0 and manufactured by GLOBALFOUNDRIES. Let’s not forget that it was in 2021 when the contract between GF and AMD happened to manufacture IO Die for CPUs built by AMD chiplets.

With the arrival of the fifth generation of DDR memory and PCI Express, a new type of I/O Die is needed, and the intention to increase the number of cores was also known. But, all the speculation was in the direction of increasing the number of cores per CCD from the eight that Zen 3 has to a higher number. In the end, the number is going to remain at eight cores per CCD.

It does not rule out the changes that AMD will implement in Zen 4, such as the already known increase in IPC and other improvements that have yet to be announced. In any case, it makes sense that AMD would decide to limit the size of the CCDs in terms of the number of cores to increase core throughput. The new IO Die will most likely not be manufactured at 5nm but with a less advanced node such as TSMC’s 7nm or other.

 
AMD Ryzen 7000: In principle there will be no increase of cores

Because the same CCDs, chiplets with CPU cores and their caches, are used in desktop AMD Ryzen as in AMD EPYC and the monolithic versions for notebooks. So, the conclusion is that we are not going to see an increase in the number of cores in principle at the domestic level. Unless, of course, AMD offers versions with 3 CCDs instead of 2 in the future Ryzen 7000, something we don’t know at the moment.

So, while Intel will increase the total number of cores from Alder Lake, AMD will be more consistent concerning what they have already deployed in the market at the moment, with configurations very similar to those that already exist but with the corresponding architectural improvements.

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